Lattice Launches Industry-First PQC-Ready FPGA Family: MachXO5-NX TDQ
‒ Sets new standard for secure control FPGAs with full CNSA 2.0-compliant post-quantum cryptography, crypto-agility, and hardware root of trust for next-generation infrastructure ‒
“Quantum computing advances increase the urgency to adopt quantum-resistant security across every industry,” said
The Lattice MachXO5-NX TDQ FPGA family equips customers with:
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Full Suite of CNSA 2.0 Compliant PQC
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First and only complete CNSA 2.0 and
National Institute of Standards and Technology (NIST)-approved PQC algorithms (LMS, XMSS, ML-DSA, ML-KEM, AES256-GCM, SHA2, SHA3, SHAKE) for robust protection against quantum threats - Authenticated and/or encrypted bitstream ensuring data integrity and protection against unauthorized access with ML-DSA, LMS, XMSS, AES256
- Unique, patent pending crypto-agility with in-field algorithm update capability and anti-rollback version protection to enable ongoing alignment with evolving standards
- Secure bitstream key management with revokable root keys and sophisticated key hierarchy for both PQC and classical keys
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First and only complete CNSA 2.0 and
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Advanced Cryptography
- Full complement of advanced symmetric and classical asymmetric cryptographic algorithms (AES-CBC/GCM 256 bit, ECDSA-384/521, SHA-384/512, RSA 3072/4096 bit) for bitstream and user data protection
- Device Identifier Composition Engine (DICE), Security Protocol and Data Model (SPDM), and Lattice SupplyGuard™ capable, providing attestation and secure lifecycle/supply chain management for future-proof, end-to-end security
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Hardware Root of Trust (RoT)
- Trusted single-chip boot with integrated flash
- Unique device secret (UDS) ensuring distinct device identity
- Integrated non-volatile configuration memory and user flash memory (UFM) with flexible partitioning and secure locking
- Comprehensive locking control of programming interface (SPI, JTAG), providing complete protection
- Side Channel Attack (SCA) resiliency and NIST Cryptographic Algorithm Validation Program (CAVP) compliant algorithms
Lattice also expanded its RoT-enabled Lattice MachXO5-NX device family with new MachXO5-NX TD devices that offer new density and package options. These new Lattice MachXO5-NX TDQ and MachXO5-NX TD FPGA devices are available and have shipped to industry-leading Communications and Compute customers, and are supported by the latest release of Lattice Radiant™ design software.
Experience Lattice PQC-Ready Innovation at OCP Global Summit
Lattice will showcase live demonstrations of its latest FPGA solutions including the MachXO5-NX TDQ for secure, AI-optimized datacenter infrastructure at the OCP Global Summit, taking place Oct. 14–16, 2025 at the
Supporting Resources
- For more information about Lattice MachXO5-NX TDQ, visit product webpage, read the launch blog, or download the white paper here.
- For more information about Lattice’s OCP Global Summit participation, read the event announcement.
- For more information about Lattice, please visit https://www.latticesemi.com
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