Cadence Collaborates With TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production DesignSource: Business Wire
- Cadence digital, signoff and custom/analog tools achieve latest DRM and SPICE certifications, and Cadence IP is enabled for TSMC 5nm process technology to advance mobile, HPC, 5G and AI application design
- Continued collaboration with TSMC resulted in delivery of Cadence IP and integrated tools, flows and methodologies that support both traditional and cloud-based environments
- Customers have successfully completed tapeouts using Cadence’s tools, flows and IP for full production development on TSMC’s 5nm process technology
To learn more about the Cadence full-flow digital and signoff advanced-node solutions, visit www.cadence.com/go/tsmc5nmds. For information about the Cadence custom/analog advanced-node solutions, visit www.cadence.com/go/tsmc5nmca. For information about Cadence IP, visit www.cadence.com/go/tsmc5nmip.
5nm Digital and Signoff Tool Certification
Cadence delivered a fully integrated digital implementation and signoff
tool flow, which has been certified on TSMC’s industry-leading 5nm
process that has the benefits of process simplification provided by
extreme ultraviolet (EUV) lithography. The Cadence full-flow includes
the Innovus™ Implementation System, Liberate™
Characterization Portfolio, Quantus™ Extraction Solution,
The Cadence digital and signoff tools that have been optimized for TSMC’s 5nm process technology provide EUV support at key layers and associated new design rules, which enable mutual customers to reduce iterations and achieve performance, area, and power (PPA) improvements.Some of the newest enhancements for the 5nm process include predictive via-pillar-aware synthesis structuring with the Genus™ Synthesis Solution as well as a pin-access control routing method for cell electromigration (EM) handling in the Innovus Implementation System and Tempus ECO and also statistical EM budgeting analysis support in the Voltus™ IC Power Integrity Solution. The newly certified Pegasus Verification System supports 5nm rule decks for all TSMC physical verification flows including DRC, LVS and metal fill.
5nm Custom/Analog Tool Certification
The Cadence custom/analog tools certified on TSMC’s industry-leading 5nm process technology include the Spectre® Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre RF Option, Spectre Circuit Simulator, Voltus-Fi Custom Power Integrity Solution, Pegasus Verification System as well as the Virtuoso® custom IC design platform, which includes the Virtuoso Layout Suite EXL, Virtuoso Schematic Editor and Virtuoso ADE Product Suite.
The Virtuoso R&D team has an ongoing and rich collaboration with the
The new Virtuoso Advanced-Node and Methodology Platform (ICADVM 18.1) consists of features and functionality required for creating 5nm designs, which include an accelerated, row-based custom placement and routing methodology that enables users to improve productivity and better manage complex design rules. Cadence introduced several new features that support the 5nm process including stacked gate support, universal poly grid snapping, area-based rule support, asymmetric coloring and voltage-dependent rule support, analog cell support and support for various new devices and design constraints that are part of TSMC’s 5nm technology offering.
5nm IP Enablement
Cadence is developing a differentiated advanced-node IP portfolio to support TSMC’s 5nm process, which includes a high-performance memory subsystem, very high-speed SerDes and high-performance analog to meet the demands of HPC, machine learning (ML) and 5G base stations. With the release of TSMC’s 5nm design infrastructure, Cadence and TSMC are actively engaged with customers and enabling next-generation SoC development by addressing the latest IP requirements for evolving application areas.
“TSMC’s 5nm technology offers our customers the industry’s most advanced
technology to address the growing demand for computing power driven by
AI and 5G,” said
“We’re continuing to broaden our collaboration with TSMC to facilitate
5nm FinFET adoption, giving customers access to the latest tools and IP
for advanced process design creation,” said Dr.
Cadence enables electronic systems and semiconductor companies to create
the innovative end products that are transforming the way people live,
work and play. Cadence software, hardware and semiconductor IP are used
by customers to deliver products to market faster. The company’s System
Design Enablement strategy helps customers develop differentiated
products—from chips to boards to systems—in mobile, consumer, cloud
datacenter, automotive, aerospace, IoT, industrial and other market
segments. Cadence is listed as one of
For more information, please contact: