Cadence Revolutionizes Verification Productivity with the Verisium AI-Driven Verification Platform
New generation of multi-run, multi-engine tools leverages big data and AI to optimize verification workloads, boost coverage and accelerate root cause analysis of design bugs on complex SoCs
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As SoC complexity continues to rise, verification has become a critical path for system time to market, often consuming significantly more compute and human resources than any other silicon engineering task. The release of the Verisium platform represents a generational shift from single-run, single-engine algorithms in electronic design automation (EDA) to algorithms that leverage big data and AI to optimize multiple runs of multiple engines across an entire SoC design and verification campaign. By deploying the Verisium platform, all verification data, including waveforms, coverage, reports and log files, are brought together in the Cadence JedAI Platform. Machine learning (ML) models are built and other proprietary metrics are mined from this data to enable a new class of tools that dramatically improve verification productivity. Using the Cadence JedAI Platform, Cadence is able to unify its computational software innovations in data and AI across Verisium AI-driven verification to Cadence Cerebrus™ Intelligent Chip Explorer’s AI-driven implementation and Optimality™ Intelligent System Explorer’s AI-driven system analysis.
The initial suite of apps available in the Verisium platform are as follows:
- Verisium AutoTriage: Builds ML models that help automate the repetitive task of regression failure triage by predicting and classifying test failures with common root causes.
- Verisium SemanticDiff: Provides an algorithmic solution to compare multiple source code revisions of an IP or SoC, classify these revisions and rank which updates are most disruptive to the system's behavior to help pinpoint potential bug hotspots.
- Verisium WaveMiner: Applies powerful AI engines to analyze waveforms from multiple runs and determine which signals, at which times, are most likely to represent the root cause of a test failure.
- Verisium PinDown: Integrates with the Cadence JedAI Platform and industry-standard revision control systems to build ML models of source code changes, test reports and log files to predict which source code check-ins are most likely to have introduced failures.
- Verisium Debug: Delivers a holistic debug solution from IP to SoC and from single-run to multi-run, offering fast and comprehensive interactive and post-process debug flows with waveform, schematic, driver tracing and SmartLog technologies. Verisium Debug is natively integrated with the Cadence JedAI Platform and other Verisium apps to enable AI-driven root cause analysis with the support of simultaneous automatic comparison of passing and failing tests.
- Verisium Manager: Brings Cadence’s full flow IP and SoC-level verification management solution with verification planning, job scheduling, and multi-engine coverage natively onto the Cadence JedAI Platform and extends it to support AI-driven testsuite optimization to improve compute farm efficiency. Verisium Manager also integrates directly with other Verisium apps, enabling interactive push-button deployment of the complete Verisium platform from a unified browser-based management console.
“AI and big data are transforming the world around us,” said
The Verisium AI-Driven Verification Platform is part of the Cadence verification full flow, which includes Palladium® Z2 emulation, Protium™ X2 prototyping, Xcelium™ simulation, the Jasper™ Formal Verification Platform and the Helium™ Virtual and
“MediaTek’s innovative SoCs across mobile, smart home, connectivity and IoT products continue to grow in complexity to meet increasing performance demands from customers. With this growth, functional verification becomes an even more critical part of our project schedules. We share Cadence’s vision for a new generation of AI-driven multi-run technologies that transform verification productivity. Our tight collaboration with Cadence confirms the Verisium platform’s groundbreaking ability to automatically accelerate the effort to root cause bugs, and we are working with Cadence to expand deployment across our IP and SoC verification teams.”
“As SoC complexity continues to grow, SoC-level verification has become a rate-limiting step in our tapeout schedules. We see a great opportunity to leverage AI and big data to dramatically improve design and verification productivity. We are working closely with Cadence to deploy the Verisium platform on our mobile SoC designs and are already seeing impressive results to automatically triage and root cause bugs.”
“Functional verification has continued to be a major concern to address the rapidly growing complexity of IP and SoC designs in STM32 Microcontrollers. Cadence’s data-driven functional verification platform and apps leveraging AI technology are a very promising approach to contain this problem. ST and Cadence have a strong vision match, which has led to a tight collaboration to deploy multiple Verisium apps at ST. We have already observed a significant boost to functional verification productivity, leveraging Verisium AutoTriage, SemanticDiff and WaveMiner. Using the Verisium apps and the Cadence JedAI Platform, we aim to quickly achieve a dramatic productivity improvement in triaging and localizing bugs on our IP and SoC designs.”
- Mirella Negro Marcigaglia, STM32 Digital Verification Manager, STMicroelectronics
Cadence is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row,