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Cadence Design Systems Inc

Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications

Highlights:

  • Significantly expanded portfolio of Cadence design IP optimized for Intel's advanced technologies
  • AI-driven digital and analog/custom EDA solutions certified for Intel 18A technology PDK, delivering optimized PPA
  • Co-developed advanced packaging reference design flow for Intel Foundry’s EMIB and EMIB-T technology certified for latest PDK
  • Engagement underway on early design technology co-optimization for Intel 14A-E
  • Joins the Intel Foundry Chiplet Alliance as a founding member

 

SAN JOSE, Calif.--(BUSINESS WIRE)--Apr. 29, 2025-- Cadence (Nasdaq: CDNS) today announced a significant expansion of its portfolio of design IP optimized for Intel 18A and Intel 18A-P technologies and certification of Cadence® digital and analog/custom design solutions for the latest Intel 18A process design kit (PDK). These advancements are being showcased today at Intel Foundry Direct Connect, underscoring Cadence’s continued leadership in driving industry innovation for artificial intelligence and machine learning (AI/ML), high-performance computing (HPC) and advanced mobility applications through its strategic partnership with Intel Foundry.

Cadence has collaborated closely with Intel Foundry to design and optimize a comprehensive range of solutions that fully leverage the innovative features of the Intel 18A/18A-P nodes, including RibbonFET Gate-all-around transistors and PowerVia backside power delivery network. With this collaboration, joint customers can achieve exceptional power, performance and area (PPA) efficiencies, accelerating time to market for cutting-edge system-on-chip (SoC) designs.

The latest additions to Cadence’s broad portfolio of design IP in Intel 18A/18A-P technologies are available shortly and include:

  • 224G SerDes with long-range performance for Universal Accelerator Link™ (UALink™) and Ultra Ethernet™, the latest standards for scaling up and out accelerator networks in AI factories
  • DDR5 – 12.8G with MRDIMM Gen2 support, supporting the latest in DRAM technology for AI applications
  • Universal Chiplet Interconnect Express™ (UCIe™) 1.1 48G, which seamlessly facilitates multi-die system-in-package (SiP) integration for scalable chiplet architectures at high data rates
  • Advanced computing and peripheral connectivity IP compatible with the latest consumer standards, enabling scalable embedded applications for a wide range of consumer and mobility requirements:
    • 10G multi-protocol SerDes PHY, supporting PCI Express® (PCIe®) 3.0, DisplayPort and Ethernet
    • eUSB2 v2.0
    • MIPI® SoundWire® I3S

Cadence’s expanded portfolio also includes a range of design IP already available in the Intel 18A technology family: 112G Extended Long-Reach SerDes with superior bit error rate (BER) performance for robust data integrity over longer distances; 64G MP PHY for PCIe 6.0, CXL 3.0 and 56G Ethernet; LPDDR5X/5 – 8533 Mbps with multi-standard support; and UCIe 1.0 16G for advanced packaging. Mutual customers now have a broad range of IP options for their AI/ML, HPC and mobility applications leveraging Intel 18A/18A-P RibbonFET and PowerVia implementation.

In addition to the new IP for Intel 18A and 18A-P technologies, Cadence’s comprehensive suite of AI-driven design and analog/custom design solutions has been certified for the latest Intel 18A node PDK. This includes the complete AI-driven Cadence RTL-to-GDS flow, featuring a range of robust solutions such as the Cadence Cerebrus® Intelligent Chip Explorer, Genus™ Synthesis Solution, Innovus™ Implementation System, Quantus™ Extraction Solution, Quantus Field Solver, Tempus™ Timing Solution and Pegasus™ Verification System. The flow also includes custom IC design solutions such as Cadence Virtuoso® Studio, the integrated Spectre® Platform and the Voltus™-XFi Custom Power Integrity Solution.

Meanwhile, Cadence and Intel Foundry are engaging in early design technology co-optimization for Intel 14A-E to establish the readiness of Cadence EDA flows for the next-generation advanced node.

In addition, Cadence and Intel Foundry have also partnered to develop an advanced packaging workflow leveraging Embedded Multi-die Interconnect Bridge-T (EMIB-T) technology. This solution streamlines the integration of complex multi-chiplet architectures—eliminating data conversion, shortening design cycles and enabling concurrent activities with early thermal, signal integrity and power modeling. It also ensures compliance with standards, reduces risks and simplifies adoption of Intel technology.

Continuing its support of the Intel Foundry Accelerator Alliance Program, Cadence has joined the Intel Foundry Chiplet Alliance Program as a founding member to ensure its solutions will help provide an assured and scalable path for customers looking to deploy designs that leverage interoperable and secure chiplet solutions for targeted applications and markets. Cadence is already a participating member in the EDA, IP, Design Services and USMAG Alliances.

“Cadence is at the forefront of facilitating next-generation AI, HPC and mobility designs with Intel 18A and 18A-P technologies, and our collaboration ensures that our mutual customers can leverage our robust design IP and AI-driven digital and analog/custom solutions for unparalleled performance and efficiency,” said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. “Our expanded design IP portfolio for Intel Foundry builds on our commitment to delivering best-in-class silicon solutions, and our advanced implementations of leading standards are key to achieving scalable, high-performance designs. We look forward to continuing to partner with Intel Foundry to build out IP solutions for the AI factories and compute platform needs of the future as well as today.”

“As we optimize solutions through our ongoing collaboration, the combination of Cadence's innovative IP solutions and Intel 18A and 18A-P technologies delivers advantages for AI/ML and HPC applications,” stated Suk Lee, vice president and general manager, Ecosystem Technology Office at Intel Foundry. “Working together, we are accelerating the development of high-performance solutions, including for chiplets, that meet the evolving needs of the industry and empower our mutual customers to drive PPA efficiencies and accelerate time to market for their innovative next-generation SoC designs.”

For more information about Cadence and its collaboration with Intel Foundry, please visit the Intel Foundry partner webpage.

About Cadence

Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.

© 2025 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. MIPI and SoundWire are registered trademarks owned by MIPI Alliance. PCI Express and PCIe are registered trademarks of PCI-SIG. Universal Chiplet Interconnect Expressand UCIe are trademarks of UCIe Consortium. All other trademarks are the property of their respective owners.

Category: Featured

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Cadence Newsroom
408-944-7039
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Source: Cadence Design Systems, Inc.