Company Announcements

Expanding partnership enables Cadence’s Design for AI and AI for Design strategy across TSMC’s N3, N2, A16 and A14 process nodes​

• Developing “agent‑ready” digital and analog flows that integrate agentic AI to enable goal‑driven PPA, reliability and productivity optimization.
• Cadence’s TSMC‑certified digital, custom/analog, 3D‑IC and signoff platforms reduce design iterations and time to tapeout.
• Strong customer momentum designing on TSMC’s 3nm and 2nm technologies underscores the collaboration’s broad market impact.

SAN JOSE, Calif.--(BUSINESS WIRE)--Apr. 22, 2026-- Cadence (Nasdaq: CDNS) today announced an expansion of its longstanding relationship with TSMC to accelerate AI-driven semiconductor innovation. The expanded collaboration will deliver IP, signoff-ready, end-to-end design infrastructure, and advanced, certified flows for leading-edge AI silicon on TSMC’s N3, N2, A16™ and A14 process technologies. The companies’ enhanced work will help customers reduce iterations and improve correlation for DTCO-focused advanced AI and HPC designs—accelerating time to silicon with greater confidence. Customer momentum underscores the impact of this collaboration, with many early and mainstream companies actively designing on TSMC’s 3nm or 2nm technologies.​

“AI silicon innovation at advanced nodes demands a signoff-ready approach that spans the full design cycle and scales from SoCs to chiplet and 3D-IC architectures,” said Chin-Chi Teng, senior vice president and general manager, Cadence. “Through collaboration with TSMC, we’re advancing our Design for AI and AI for Design strategy by uniting certified flows with silicon-proven IP and building the agent-ready foundation that will help engineers improve productivity as complexity continues to rise.”

"The growing demands of AI compute workloads, combined with compressed design cycles, require advanced, energy-efficient silicon technologies, streamlined design flows, and silicon-validated IPs," said Aveek Sarkar, Director of the Ecosystem and Alliance Management Division at TSMC. "Through our collaboration with Open Innovation Platform® (OIP) ecosystem partners like Cadence, we empower customers to confidently design cutting-edge silicon using TSMC’s latest process technologies and 3DFabric® advanced packaging solutions —unlocking transformative opportunities for AI-driven innovation."

Design for AI: Silicon-Proven IP, and Certified, End-to-End Flows

Cadence is delivering a rich IP portfolio for TSMC N2P, including DDR5 12.8G MRDIMM, PCIe® 6.0, LPDDR6/5X 14.4G and HBM4E 16G. The Cadence® Artisan® foundation IP advanced-node portfolio is now in production designs using TSMC N3 process technologies.

Cadence enables semiconductor teams with certified, end-to-end EDA flows that scale from advanced-node SoCs to chiplet and 3D-IC designs, including implementation with the Innovus^™ Implementation System; custom/analog implementation and simulation with Virtuoso® Studio and the Spectre® Simulation Platform; thermal analysis with the Celsius^™ Thermal Solver, Voltus^™ IC Power Integrity Solution, and EMX^® Planar 3D Solver; and signoff technologies with Tempus^™ Timing and ECO Solution, Quantus^™ Extraction Solution, Liberate™ Characterization Portfolio, and Pegasus^™ Verification System; all certified for TSMC N2 and A16, and ongoing collaboration for A14 PDKs to accelerate convergence of tapeout-quality results for AI/HPC applications.​​ Additionally, the Genus Synthesis Solution is enabled for these process technologies and on-going collaboration on Clarity^™ 3D Solver.

For 3D-IC and heterogeneous integration, the Cadence Integrity™ 3D-IC Platform supports the TSMC-COUPE™ Reference Flow for stacked-die, while Virtuoso Studio’s heterogeneous integration methodology adds silicon photonics support. Celsius thermal-aware flow is enabled including PIC placement with Virtuoso and signal integrity analysis with EMX. It also features quality checks and physical verification with the Pegasus Verification System for heterogeneous systems.

AI for Design: “Agent-Ready” Infrastructure

Cadence’s agentic AI boosts productivity in AI semiconductor and 3D-IC design by shifting EDA from tool-by-tool workflows to goal-driven, agentic execution. Working with TSMC, Cadence is preparing “agent-ready” design flows, optimization engines, and signoff infrastructure. These capabilities enable AI systems to combine domain reasoning with physics-based analysis, driving convergence of PPA and reliability tradeoffs across all aspects of design.

“The increasing scale and complexity of next-generation AI silicon require a reinvented approach to design that integrates accelerated computing and agentic AI at every stage of the chip design cycle,” said Tim Costa, vice president and general manager of computational engineering at NVIDIA. "By collaborating with Cadence, NVIDIA is helping advance the EDA tools necessary for its design teams and the global semiconductor ecosystem to optimize performance and accelerate the delivery of the world's most sophisticated AI architectures."

The enhanced Genus Synthesis Solution, Innovus Implementation System, and Cadence Cerebrus^® Intelligent Chip Explorer’s AI-driven implementation is optimized to support TSMC NanoFlex™ Pro standard cell architecture for DTCO, enabling fine-tuning speed and power efficiency during floorplan and placement. In addition, front-end placement and back-end routing rules improve correlation between pre-route and post-route results; and TSMC’s A16 Super Power Rail enables denser and faster designs by routing power nets on the backside of the chip.​

In custom design, Cadence has embedded agentic AI in Virtuoso Studio flows with circuit optimization for TSMC process technologies. This includes the enablement for N2-to-A14 Analog Design Migration flow.​

Customer Momentum at 3nm and 2nm

Customers are successfully designing silicon on TSMC’s 3nm and 2nm technologies, reflecting broad adoption across the AI and high-performance computing ecosystem. This mutual customer momentum reinforces the role of certified flows, silicon-proven IP, and signoff-ready infrastructure in enabling faster, more confident delivery of next-generation AI silicon.​

“As AI and high-performance computing workloads grow, there is increasing demand for efficient compute platforms that can be delivered at advanced process nodes,” said Eddie Ramirez, vice president of go-to-market, Cloud AI Business Unit at Arm. “Collaboration within the ecosystem—including between leading design and manufacturing partners such as Cadence and TSMC—plays an important role in enabling the next generation of Arm-based infrastructure for AI and HPC deployments.”

"Positron is building a purpose-designed AI inference accelerator chip optimized for transformer workloads that demands both leading-edge process technology and high-bandwidth connectivity," said Thomas Sohmers, CTO at Positron. "By licensing Cadence's PCIe 6.0 SerDes IP on the TSMC N3P process node, we are able to integrate silicon-proven, high-speed interfaces with confidence. The Cadence-TSMC partnership and Cadence's front-end tooling, including Genus Synthesis Solution and Innovus Implementation System, gives us a dependable, mature and highly predictable path to tapeout—exactly what we need as we bring our second-generation inference accelerator rapidly to market."

About Cadence

Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.

© 2026 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks

CATEGORY: FEATURED

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Steve Gartner
513-479-4060
sgartner@cadence.com

Source: Cadence Design Systems, Inc.